SiSoftware Sandra Lite

Camel1965

Bardzo aktywny
Zasłużony
Dołączył
8 Wrzesień 2010
Posty
37247
Reakcje/Polubienia
33662

SiSoftware Sandra 2021 R13a Build 31.89

SiSoftware Sandra 20/21-R13a Build 31.89:


  • Hardware
    • Intel Future Server
    • Intel Atom “Elkhart Lake” ELK
    • Intel 3rd gen Xeon “Whitley”/”Ice Lake” Server (“Ice Lake”) ICL-SP
      • fixed crashes on all benchmarks
    • AMD Ryzen 6000 (Mobile) platform preliminary support
  • Benchmarks
    • Memory Bandwidth Benchmark
      • fixed failure with Atom/SSE2-4 code path
    • Cache Bandwidth Benchmark
      • fixed failure with multiple cores/threads CPUs (e.g. ICL-SP)
      • tested up to 16 NUMA, 112C / 224T, up to 1024T supported.
    • Multi-Media Benchmark
      • AMD EPYC – we’re tracking an issue on 2S / 128C / 256T servers that may result in incorrect scores.
  • Client (GUI)
    • Light/Dark-mode font optimisations
    • Icon dynamic colour customisation
Zaloguj lub Zarejestruj się aby zobaczyć!
 

Camel1965

Bardzo aktywny
Zasłużony
Dołączył
8 Wrzesień 2010
Posty
37247
Reakcje/Polubienia
33662
SiSoftware Sandra 2021 R14c Build 31.96
  • Memory Latency Benchmark
    • In-Page Random” memory access latency pattern – TLB range fix – that resulted in too-low memory score (latency) to be reported on modern Intel systems (e.g. AlderLake with large L3 cache).
    • Better random number generator (2^32 vs. 2^15 states) in order to defeat any possible sequence detection.
    • Note that the other tests “Full Random” and “Sequential” memory access patterns – are *not* affected as the pattern is not affected by TLB data.
    • It is always recommended to use “2MB/large” pages rather than “4kB/normal” pages in order to minimise TLB miss penalties which is the reason for the “in-page random” test.
    • Reverted to testing latencies of all cores (thus “Multi-Core”) rather than just 1 thread/core (“Single-Core”) so that on hybrid systems (Alder Lake, Raptor Lake, etc.) the average/overall latency does not favour just to Big/P cores.
  • Cryptography Benchmark
    • fixed HWA code paths (AES, SHA) not engaging [R13x regression]
  • Hardware
    • Resolved L2 & L3 cache count detection [R13x regression]
  • Client (GUI)
    • Light/Dark-mode colour optimisations
Zaloguj lub Zarejestruj się aby zobaczyć!
 

Camel1965

Bardzo aktywny
Zasłużony
Dołączył
8 Wrzesień 2010
Posty
37247
Reakcje/Polubienia
33662
SiSoftware Sandra Lite R15 (2021.12.31.98)
July 22, 2022
  • Benchmarks, Hardware Support updates and fixes
  • CUDA GP-GPU Benchmarks:
  • Updated to CUDA SDK 11.8 with nVidia Ada support [GeForce RTX 4090, etc.]
  • Memory Bandwidth Benchmark:
  • 3-5% bandwidth increase due to L1D block/prefetch optimisations [e.g. AVX512 AMD Zen4, Intel ICL-SP, future arch.]
  • Memory Latency Benchmark:
  • “In-Page Random” memory access latency pattern – additional TLB ranges randomisation in addition to the randomisation within each TLB range. Credit Rob Williams @ TechGage – many thanks!
  • Benchmark now fails (does not run at all) if TLB information cannot be detected, e.g. CPU does not report it.
  • This change affects both Data and Code latencies.
  • Note that the other tests “Full Random” and “Sequential” memory access patterns – are *not* affected – as the pattern is not affected by TLB data.
  • It is always recommended to use “2MB/large” pages rather than “4kB/normal” pages in order to minimise “TLB miss” penalties which is the reason for the “in-page random” test. Please see How to enable large/huge memory pages in Windows.
  • Cryptography Benchmark:
  • 3-5% bandwidth increase due to L1D block/prefetch optimisations [e.g. AVX512-VAES AMD Zen4, Intel ICL-SP, future arch.]
  • Client (GUI):
  • Light/Dark-mode colour optimisations
Zaloguj lub Zarejestruj się aby zobaczyć!
 

Camel1965

Bardzo aktywny
Zasłużony
Dołączył
8 Wrzesień 2010
Posty
37247
Reakcje/Polubienia
33662
SiSoftware Sandra Lite R18 (2021.12.31.112)
November 19, 2022
  • Gp-GPU Performance:
  • nVidia 4090 series FP16 validation failure (too low precision for image size)
  • nVidia CUDA 90 / 89 support
  • Gp-Gpu Memory Bandwidth:
  • Corrected DirectX Compute (11/12) bandwidths with some internal graphics
  • Memory Detection:
  • Intel XMP 30, AMD EXPO DDR5 detection missing in some instances
  • Jedec, Intel XMP 20 DDR4 write timings if provided by newer standard revision
  • Corrected timings (tRP, tRAS) for some Intel ADL/RPL systems
  • Missing memory timings for some mobile Intel ADP-P/U systems
  • Added support for more chipsets (both AMD and Intel)
Zaloguj lub Zarejestruj się aby zobaczyć!
 

Camel1965

Bardzo aktywny
Zasłużony
Dołączył
8 Wrzesień 2010
Posty
37247
Reakcje/Polubienia
33662

SiSoftware Sandra Lite R25 (2021.12.31.133)​

August 7, 2023
  • CPU Multi-Media Benchmarks:
  • AVX-iFMA(52): New 256-bit code path based on AVX512-iFMA(52) 512-bit for future arch (e.g. “Meteor Lake” MTL, “Arrow Lake” ARL). We saw +66% improvement as detailed in our AVX512-iFMA(52) Improvement for IceLake and TigerLake article.
  • AVX512-FP16: New code path for Xeon processors that support AVX512-FP16. We expect +90% improvement over FP32 if precision loss in acceptable (e.g. zoomed out fractals).
  • Note: Future FP16 code-paths will also be added to the other CPU benchmarks, however some parts may remain FP32 as the loss of precision would make the results useless. We have explored this in our GP-GPU article dealing with FP16 support: FP16 GP-GPU Image Processing Performance & Quality.
  • CPU Cryptogaphy Benchmarks:
  • SHA2-512 HWA: Hardware-accelerated hashing SHA512 code-path – based on current SHA2-256 HWA. We expect ~3x (three times) better performance based on the SHA2 non-accelerated/HWA results.
  • Future SM3-256 (China) HWA: Hardware-accelerated hashing SM3 code-path (China’s version of SHA hashing functions). We expect similar performance improvement to SHA HWA.
  • Future SM4-128/256 (China) HWA: Hardware-accelerated block crypto SM4 code-path (China’s version of AES block crypto functions). We expect similar performance improvement to AES HWA.
  • Note: We will default to “SM4 + SM3” benchmarks – rather than “AES + SHA” for both CPU & GP-GPU Cryptography benchmarks when “China” locale is detected as these algorithms are more likely to be used there.
  • Note 2: ARM already includes SHA2-512, SM4, SM3 HWA (hardware acceleration extensions) in their high-end cores.
  • Note 3: While AES & SHA are not going anywhere, there has been a shift to other crypto-algorithms (especially those that can encrypt/decrypt and hash/authenticate like “ChaCha20Poly1305” as famously used in WireGuard VPN) that are fast enough even without hardware acceleration!
  • All CPU Benchmarks – AVX10 Support:
  • AVX10.2+ 256-bit future code paths (FP32, FP64 and FP16) for Hybrid architectures (e.g. “Meteor Lake” MTL, “Arrow Lake” ARL). Note both Core (P) and Atom (E) will run the same 256-bit width binary and not different widths
  • AVX10.1+ 512-bit & AVX512 shared code path (FP32, FP64 and FP16) for Xeon architectures
  • Possible AVX10.2+ 128-bit future code path for Atom/Other discrete architectures if required
  • Note: in future Hybrid arch, Core (P) cores are likely to support 128/256-bit widths only. We don’t know (and we could not tell you) whether disabling Atom (E) cores will get the Core (P) to report 512-bit widths.
  • Hardware Support:
  • Intel 14th gen Hybrid “Raptor Lake Refresh” RPL-S support
  • Intel future gen Hybrid “Meteor Lake” (MTL-S/M/P/N), “Arrow Lake” (ARL-S/U), “Lunar Lake” (LNL-M) detection
  • Intel future gen Xeon “Granite Rapids” SP/D detection
Zaloguj lub Zarejestruj się aby zobaczyć!
 

Camel1965

Bardzo aktywny
Zasłużony
Dołączył
8 Wrzesień 2010
Posty
37247
Reakcje/Polubienia
33662
SiSoftware Sandra Lite 2021.12.31.137

SiSoftware Sandra 20/21-R26 Build 31.137:


Hardware Support​


  • Resolved detection issues with Intel’s 14th Gen Core RaptorLake-Refresh (e.g. 14700K(F))
  • Resolved reporting issues with AMD’s Gen4 Ryzen (e.g. 7950X-3D)

Software Support​


  • Resolved detection issues with tiered Storage Pools (e.g. Windows’ Storage Spaces)
  • Updated Official Ranker API for greater reliability

Windows Defender Core Isolation features and Sandra’s Kernel Driver​


Sandra is compatible with most “Core Isolation” security features and you can have those enabled:


  • Memory Integrity – Compatible, can enable
  • Memory Access Protection – Compatible, can enable
  • Microsoft Vulnerable Driver Blocklist – Kernel driver compatible
  • Kernel-mode Hardware-enforced Stack Protection – Kernel driver not compatible, but software will still run with reduced functionality
Zaloguj lub Zarejestruj się aby zobaczyć!
 
Do góry