MEMTEST86/86+

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Memtest86 4.3.1

info:dobreprogramy.pl

Bardzo dobry program do testowania kości pamięci RAM w komputerze. Pamięć (zwłaszcza ta gorszej klasy) jest obok samego systemu operacyjnego najczęstszym elementem, który może mieć wpływ na niestabilną pracę komputera. Jeżeli więc komputer nie pracuje prawidłowo, zawiesza się, pojawiają się różnego rodzaju "śmieci" na ekranie, powinniśmy w pierwszym rzędzie skorzystać z tego programu. Memtest86 pracuje całkowicie niezależnie - tworzy dyskietkę startową z programem, z której później uruchamiamy komputer i sam program. Program testuje pamięć za pośrednictwem kilkunastu algorytmów.

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Re: MEMTEST86

Memtest86 4.3.2

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· Memory bandwidth is now measured for one CPU (as opposed to being a total for all CPUs & Cores). This will lower the reported bandwidth for multi-core machines. But we think it makes more sense this way.
· Fixed crash when attempting to boot on older single core machines with hyperthreading. Only effects old machines, from around the early Pentium 4 era, that didn't have a MP (Multi-Processor) Spec table defined but did have both a MADT (Multiple APIC Description Table) defined and hyperthreading enabled.
· Restored the "Start only one CPU" boot option. This option should not be required in normal use, but might be useful for debugging purposes.
· Updates to the included help file

 

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Re: MEMTEST86

Memtest86 4.3.3

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· Fixed incorrect progress calculation for test 4
· Fixed potential false positives in parallel mode caused by overlapped/unaligned memory chunk allocations per CPU
· Fixed program freeze when selecting test 0 or 1 when running in non-parallel mode

 

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Re: MEMTEST86

Memtest86+ 5.01

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New Features:
· Added support for up to 2 TB of RAM on X64 CPUs
· Added experimental SMT support up to 32 cores (Press F2 to enable at startup)
· Added complete detection for memory controllers
· Added Motherboard Manufacturer & Model reporting
· Added CPU temperature reporting
· Added enhanced Fail Safe Mode (Press F1 at startup)
· Added support for Intel "Sandy Bridge-E" CPUs
· Added support for Intel "Ivy Bridge" CPUs
· Added preliminary support for Intel "Haswell" CPUs (Core 4th Gen)
· Added preliminary support for Intel "Haswell-ULT" CPUs
· Added support for AMD "Kabini" (K16) CPUs
· Added support for AMD "Bulldozer" CPUs
· Added support for AMD "Trinity" CPUs
· Added support for AMD E-/C-/G-/Z- "Bobcat" CPUs
· Added support for Intel Atom "Pineview" CPUs
· Added support for Intel Atom "Cedar Trail" CPUs
· Added SPD detection on most AMD Chipsets

Bug Fixes:
· Enforced Coreboot support
· Optimized run time for faster memory error detection
· Rewriten lots of memory timings detection cod
· Corrected bugs, bugs and more bugs (some could remain)

 

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Memtest86 4.3.4

· Fixed incorrect progress calculation for test 0
· Fixed incorrect memory size due to bug with memory map when the e820 entry size member is 0
· Fixed incorrect number of CPU's found due to duplicate entries in the MADT
· Changed the method used to search for processors to searching the APIC MADT first, then search the MP spec table (as opposed to vice versa). The MP spec table has largely been deprecated.

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Memtest86 4.3.5

Fixed potential error due to barrier structure located at fixed memory location
Fixed block move test freeze on higher memory addresses

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Memtest86 4.3.6

Fixed crash (particularly for AMD machines) that is seemingly resolved by adding CPU synchronication barriers before and after performing the memory speed test
Fixed an error in setting the barrier structure's base address, preventing a possible crash or freeze of the system.
Added a check to perform a spin lock only when more than 1 CPUs are detected

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Memtest86 5.0

ECC RAM support (limited hardware support, ongoing development)
Detection of ECC support in both the RAM and memory controller
Polling for ECC errors
Injection of ECC errors for test purposes. (limited hardware only)
Option to disable CPU caching for all tests
Support for reading parameters from a configuration file to allow settings to be predefined without the need for keyboard input. This can help with automation.
Support for Secure Boot
Speed improvements of between 10% and 30%+. Especially for tests, #5, #8 & #9. This is the result more moving to native 64bit code, removing the PAE paging hack, switching compilers and using faster random number generation algorithms.
Addition of 2 new memory tests to take advantage of 64bit data and SIMD instructions.
Includes changes from the previous Beta version

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Memtest86 5.1.0

Fixed ECC error detection for Ivy Bridge-E chipsets
Fixed rounding of memory SPD timings
On 32-bit systems, systems with upper address limit > 32-bits freezing during testing is now fixed
Locking memory for testing is now more robust
Added SPD support for VT8237S, Intel X79, Intel NM10 Chipsets
Fixed incorrect decoding of # of banks in DDR2 FB SPD causing the memory stick size to be reported incorrectly
Increased the number of supported memory modules from 16 to 32
Increased the maximum number of SMBus controllers to 8
DDR3 revision 1.3 SPD decoding now supported
Fixed SMBUS CLK issues when retrieving SPD details for Intel chipsets
CPU spec updates, AMD Kaveri + Intel Haswell refresh
Xeon (Ivy Bridge and later) non-Turbo CPU speeds now recorded.
Minor temperature reporting changes for AMD Family 15h, Models 0h-0Fh and 30h-3Fh (e.g. A10-7850K)
Fixed "Pass" progress bar so that it shows 100% on completion of one pass
A notification text is now displayed when ECC errors are injected
Improved notificaion text displayed when ECC errors are detected
Updated MemTest86 BIOS version to 4.3.7

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Memtest86 6.0.0

New Features:
Support for DDR4 RAM (and associated hardware), including retrieval and reporting of DDR4-specific SPD details. This includes DDR4 RAM that support Intel XMP 2.0 DDR4 RAM timings.
New RAM benchmarking feature allowing results to be graphed and saved to disk. Previous results can be graphed on the same chart for comparison.
New "Hammer Test" for detecting disturbance errors caused by charge leakage when repeatedly accessing addresses in the same memory bank but different rows in a short period of time.
Language support for French/German/Japanese/Chinese. All text are displayed in the selected language, including generated reports.
Fixes/Enhancements:
Added Haswell-E (DDR4) ECC support
Added Xeon E5 v3 ECC support
Added Ivy Bridge (non-Xeon) ECC support
Added AMD Steppe Eagle ECC support
Added Intel Atom E3800 SoC ECC support
Fixed ECC detection for Ivy Bridge-EX/Haswell-EX chipsets that have a 2nd memory controller
Fixed Intel5400 ECC registers not being reset after starting test
Fixed ECC errors immediately being reported after starting test (Ivy Bridge-E)
Added support for ECC injection for Intel Xeon E3 v3 (untested)
Fixed handling of Intel ICH SMBUS built-in hardware semaphore to prevent SMBus device contention
Fixed possible crash when DDR3 module type value in the RAM SPD info is invalid
Fixed DDR4 SPD clock speed rounding errors in the RAM SPD info
Fixed DDR3 SPD Register manufacturer/type in the RAM SPD info not appearing correctly
CPU speed measurement is now more robust by taking multiple samples
Fixed Intel turbo clock speed calculation
Fixed detection of Intel turbo support for Xeon chipsets
Increased maximum # of supported CPUs to 72
Increased maximum # of supported RAM modules to 64
Increased the number of supported memory controllers to 8
New config file parameter 'ECCINJECT' for specifying whether to enable/disable ECC injection
New config file parameter 'MEMCACHE' for specifying whether to enable/disable memory caching
New config file parameter 'PASS1FULL' for specifying whether the first pass should run the full iteration or reduced iteration
New config file parameter 'ADDR2CHBITS' to specify the address bits to XOR to determine the memory channel
New config file parameter 'LANG' for specifying language to use on startup
Console resolution is now forced to 80 x 25
Graphics resolution is now set to a minimum of 1024 x 768
Updated ImageUSB to v1.1.1015 which includes an option to zero the USB drive
Running memory tests in parallel mode is now more robust for UEFI BIOS that exhibit inconsistent multiprocessor behaviour
Fixed detection of the number of enabled processors for UEFI BIOS that exhibit inconsistent multiprocessor behaviour
Fixed test status screen not being displayed correctly for consoles with small/large screen widths
In the RAM SPD menu screen, PGUP/PGDN can be used to navigate between pages of RAM modules
For specific cases where files under EFI\BOOT cannot be accessed (eg. grub2), log/report files shall be written to the root directory
During MemTest86 boot-up, the system memory map is now written to log file
Various optimizations of the size of the MemTest86 binary
Forced a memory address limit of 32-bits when running under 32-bit UEFI
Memory ranges to be tested are now allocated at the beginning of each test (due to the possibility that the memory map changes in the middle of testing)
Reduced the number of log messages written when waiting for other processors to finish when running in parallel mode
When allocating memory for Bit Fade Test, leave 1MB of free memory available (to prevent firmware drivers from running out of memory)
Fixed potential crash or other unexpected behaviour due to memory issues with random functions
Reports are now saved using UTF16 encoding to support Unicode characters
Changed memory allocation behaviour by only pre-allocating memory segments >= 16MB to prevent memory

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Memtest86 6.1.0

New Features:
New config file parameter REPORTNUMERRS for specifying the maximum number of errors to include in the report
Language support for Spanish
RAM details obtained from SMBIOS are now displayed if SPD information cannot be accessed
Fixes/Enhancements:
Added ECC detection support for Intel Atom C2000 SoC chipset
Added ECC injection support for Intel Atom C2000 SoC chipset
Added ECC injection support for Intel Xeon E3 (Sandy Bridge/Ivy Bridge) chipset (untested)
Added SMBus (SPD) support for Intel 5100 chipset
Added SMBus (SPD) support for Intel Wildcat Point chipset
Added SMBus (SPD) support for Intel Sunrise Point chipset
Improved speed of retrieving SPD data
Fixed potential issue with retrieving DDR4 SPD due to the bank address not being restored back to its original value
Fixed decoding of ECC support in DDR2 SPD
Added support for more precise timings supported by DDR3 rev 1.1 and later
Fixed bug with retrieving SPD details for a large number of RAM modules (ie. > 16)
Fixed the progress indicator for Test 13 (Row hammer test) to be more linear
Reduced the test time for Test 13 (Row hammer test)
Fixed the displayed error details when ECC errors are detected
Fixed freeze while initializing the screen for some firmwares due to an unsupported driver protocol
Added workaround for incorrect text length/height returned by the UEFI firmware
Added checks for the number of cores exceeding the maximum supported in MemTest86
Synchronized cache enabling/disabling across all CPUs
Migrated CPU cache info code from PerformanceTest/BurnIn Test. The displayed cache info should now be more consistent with what is displayed in BurnIn Test/Performance Test.
Fixed Enabling/Disabling of features in the Sys Info screen to be less confusing
Fixed CPU Selection screen to truncate the list of available processors when more than 16 are available
Various system info related updates/fixes (CPU)

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Memtest86 6.2.0

New Features:
The details of the errors that were detected in the first pass of the Hammer Test but not during the second pass can be displayed in the report by specifying the configuration file parameter 'REPORTNUMWARN'. This parameter represents the maximum number of warnings to display in the report file.
New configuration file parameter 'AUTOMODE' for full automation. Enabling this parameter shall result in the following:
Splash screen is skipped and the tests are started immediately
When the tests are completed, the report is saved to disk automatically
System is rebooted
Due to the high number of failures reported for the Hammer Test (Test 13), the algorithm was revised to perform 2 potential passes:
Row pairs are hammered at the maximum hammer rate. (ie. no delays between each row pair hammer)
Row pairs are hammered at a lower hammer rate (200K per 64ms, as determined by memory vendors as the worst case scenario)
If memory errors are detected in the first pass, error details are not immediately displayed to the user and the second pass is started. If errors are detected in the second pass, they are reported as normal.
If errors are detected in the first pass but not the second pass, a warning of potential high frequency bit flips is displayed to the user.
The premise behind this revision is to better inform users of the significance of errors detected in the Hammer Test, as opposed to a strict PASS/FAIL result. Although errors detected in this test are real errors, the conditions needed to induce these errors occur only very rarely in normal PC usage, and should not be of concern to most users. Therefore, a warning rather than an outright failure would ensure the user is aware of the issue and be able to take the necessary measures to mitigate the issue.
Fixes/Enhancements:
Shortened the test time for Hammer Test (Test 13) by reducing the total number of hammers per row address pair
Fixed issue with the main menu not displaying for certain EFI firmware. Due to the fact that many EFI firmwares require the use of the obsolete ConsoleControl protocol to switch between graphics/console mode, the graphics/console mode workaround is now enabled by default.
Fixed bug with details of empty RAM slots being displayed when using SMBIOS memory device information
Added Intel Skylake ECC support
Updated Jedec manufacturer ID list for displaying the vendor name from RAM SPD. Fixed Jedec manufacturer ID lookup function to support > 7 continuation codes.
Fixed AMD Hudson-2/Hudson-3 SMBus support to include various hardware revisions
Various system info related updates/fixes (SPD, CPU)

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[Camel1965]

Memtest86 6.3.0

Version 6.3.0 27/Jan/2016

New Features

New configuration file parameters MINSPDS, SPDMANUF and SPDPARTNO to specify the values that the RAM SPD must match before allowing the tests to start. This may be useful for RAM manufacturers that need to verify that the SPD data has been programmed correctly.
New configuration file parameter SKIPSPLASH to skip the 10 second splashscreen and proceed directly to the main menu
New mode for the configuration file parameter AUTOMODE to specify that MemTest86 shall run the tests immediately (skipping the splashscreen and main menu) but prompt the user to save the results after test completion
New configuration file parameters ADDR2SLBITS and ADDR2CSBITS to specify the bit positions of a memory address to exclusive-or (XOR) to determine which DIMM slot/chip select (0 or 1) corresponds to the failure address

Fixes/Enhancements

Added ECC detection support for Broadwell-H chipset
Added ECC detection support for Broadwell-DE chipset
Added ECC detection support for AMD Bald Eagle (2nd generation Embedded R-series)
Added ECC injection support for AMD Steppe Eagle/Bald Eagle
Added SMBus (SPD) support for Broadwell-DE
Fixed decoding of JEDEC manufacture names from the SPD
DDR3 XMP rev1.3 SPD decoding is now supported
Fixed retrieval of DDR4 SPD bytes for Intel ICH SMBUS
Added workaround for buggy firmware when calls to EFI MPServices fail
Fixed MemTest86 freezing on network boot
Fixed bug with wrong details being displayed for detected memory warnings in the report file
Fixed bug with CPU type detection for older CPUs
Fixed benchmark chart not being displayed after running a RAM benchmark test when there is a failure in saving results to disk
Report file now includes the RAM serial number, if available
Various system info related updates/fixes (CPU)

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Memtest86 7.0

New Features:
Row Hammer Test (Test 13) now uses double-sided hammering and random data patterns in an attempt to expose more RAM modules susceptible to disturbance errors.
PXE network boot is now fully supported (MemTest86 Site Edition only) to support scalable, diskless deployment to PXE-enabled clients. Like the Pro version, the configuration file (acquired from the PXE server via TFTP) can be used for customization and configuration of MemTest86 memory tests. Report files can also be uploaded to the server. Logging, however, is unavailable.
Memory tests are run in Parallel CPU mode by default, if supported by the UEFI firmware. Running in parallel mode significantly decreases the test time as compared to running in single CPU mode and should also help to detect more errors faster. This was made possible after developing a work around for UEFI BIOS bug that prevented multi-threading on some machines.
Added 'HAMMERPAT' config file parameter to specify the data pattern to use for the row hammer test. By default, random data patterns are used.
Added 'HAMMERMODE' config file parameter to specify whether to use single or double sided hammering. By default, double-sided hammering is used.
Added 'CPULIST' config file parameter to specify a subset of available CPUs to enable for the memory tests.
Added 'DISABLEMP' config file parameter to disable multiprocessor support in MemTest86. This can be used as a workaround for certain UEFI firmwares that have issues running MemTest86 in multi-CPU modes.
Added 'BGCOLOR' config file parameter to specify the background colour to use
Added Portuguese translations
Added Czech translations
Fixes/Enhancements:
Added ECC support for different revisions of Intel Skylake memory controllers
Fixed ECC detection on Intel Broadwell-H chipsets
Changed how ECC errors are detected on Broadwell chipsets
Changed how ECC errors are detected on Atom C2000 chipset
Fixed incorrect channel/slot number being reported for ECC errors on E5 chipsets
Added SMBUS (SPD) support for Intel Broxton
Added SMBUS (SPD) support for Intel Airmont
Added SMBUS (SPD) support for Intel Sunrise Point-LP
Reduced the number of iterations for the Modulo 20 Test (Test 9) to decrease the test time
Reduced the number of addresses to be hammered for the Row hammer Test (Test 13) to decrease the test time
When no tests are completed, the test report now displays "N/A" as oppose to "PASS"
The High Precision Event Timer (HPET) is now used to measure the clock speed, if available. Otherwise, the older Programmable Interval Timer (PIT) is used.
The clock speed displayed in the RAM info is now the effective clock speed as opposed to the actual clock speed. The effective clock speed is twice the actual clock speed for DDR RAM.
Speeds greater than 10000MB/s are converted to GB/s when displaying memory/cache speeds in the test screen
Memory sizes greater than 10240MB are now displayed in GB
Console is no longer forced to 80 x 25 if the current mode has a higher resolution
Fixed issue with certain UEFI firmware when switching from console to graphics mode
Fixed RAM benchmark chart title string overflow
Various system info related updates/fixes (CPU)

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[Camel1965]

Memtest86 v.7.1

Version 7.1 5/Aug/2016

Fixes/Enhancements

Fixed a bug in measuring CPU clock speed using HPET which could skew the clock speed results to unreasonable values. This may have caused issues during startup including extremely long loading times
Added fallback mechanism to use the legacy PIT to measure the clock speed if the measured CPU clock speed using HPET is unreasonable
Disabled code optimization for Test 12 due to reported freeze when running in parallel mode
Fixed CPU selection mode not being set according to the results of the multiprocessor test during startup
When switching to the next target CPU in Sequential/Round Robin mode, attempt to reset the target CPU if there was a failed attempt to switch the BSP
When looking for SMBus devices for RAM SPD retrieval, attempt to look for any disabled SMBus devices to enable before enumerating the PCI bus
Fixed cursor appearing for some systems during testing

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